Many electronic circuit applications require maintaining the stability of more than one sub circuit loop within a larger circuit. Challenges can arise, however, when the loop stability requirements come into conflict. For example, in some applications it is desirable to use low dropout regulators (LDOs) that have high stability at very low capacitive loads. This is attractive for reducing the cost associated with using additional external components. Also, portable applications require low dropout voltages and very low power consumption in order to accommodate battery-power limitations. A representative example of a low dropout regulator, in this case a PMOS LDO 10 known in the arts is shown in FIG. 1. A common approach to meeting these often conflicting design requirements is to use Miller compensated PMOS LDOs with quiescent current boosting techniques. Referring to FIG. 2, an example of this prior art approach is shown. The circuit 12 uses PMOS transistors to ensure low dropout. Miller compensation adds a compensation capacitor Cc because the load capacitance CL is not large enough to produce a useable dominant pole. Quiescent current boosting dependent upon sensed current output is used to conserve power under light load conditions. This is but one example of circuitry known in the arts where stability problems addressed by the invention may be used. The examples herein are presented for illustrative purposes and those skilled in the arts will recognize that the invention may be practiced in a variety of contexts requiring the stabilization of two loops.
Given a low dropout regulator (LDO), in this case a PMOS LDO 10, a current sensing circuit 14 is configured to sense the output current and limit the maximum amount of current provided by the LDO 10 in the case of a short circuit at the output, node N1, of the LDO 10. The current sensing circuit 14 is based on the use of a sense FET M2 and a sense resistor Rs. The measurement of the voltage drop across the sense resistor Rs is as a proxy for the total output current through the power transistor M3. A pull-up transistor M1 is used to pull up the gate of the power transistor M3 when a comparator 16 has detected that a predetermined threshold of maximum current has been exceeded. A buffer 18 between node N1 and node N3 is used to isolate the gate capacitance of the power transistor M3 from the high impedance at the output of the error amplifier 20. The quiescent current of the buffer 18 is dynamically boosted directly proportional to the current of the load IL in order to provide for stability. For this reason, the pull-up transistor M1 drain D1 is connected at node N1, because if connected directly to node N3, it would have to fight against the boosted output stage of the buffer 18 to pull the power device M3 gate up under current limit conditions.
By further consideration of FIG. 2 it may be seen that the current limit control loop 12 includes the comparator 16 and pull-up transistor M1, in essence forming a two-stage amplifier circuit. The common method known in the arts for compensating a two-stage amplifier circuit is to use Miller compensation. Adding a compensation capacitor Cx between node N1 and node N2 to compensate the current limit loop 22 is the standard approach. However, this compensation capacitor Cx introduces trade-offs in the performance of the LDO 10.
There are at least two general classes of difficulties with this compensation approach. First, for the purpose of example, it is assumed that the error amplifier 20 has only one gain stage. Using the example of a folded cascode, in this case the Miller compensation splits the poles at node N1, the high impedance node of a folded cascoded amplifier, and node N4. Adding the compensation capacitor Cc between node N1 and node N4 adds to the overall capacitance at the high impedance node N1 of the folded cascode. Assuming that the capacitance Cx used to compensate the current limit loop 22 is smaller than the Miller compensation capacitor Cc used for the LDO loop 10, this increased capacitance reduces the overall slew rate of the amplifier 20. The reduced slew rate is undesirable, as it degrades the transient response of the LDO 10. Alternatively, in an effort to achieve a better Power supply rejection ratio (PSRR) by using compensation to a low impedance node, connecting the compensation capacitor Cc to the source of the common gate transistor in the folded cascode instead of to high impedance node N1, the trade-offs are more severe. Not only does the transient response suffer, but also the LDO 10 may become unstable. It is desirable to keep the capacitance at node N1 to a minimum because the pole at node N1 is not split by Miller compensation. Also, since N1 is a high impedance node, any capacitance may create a significant pole that would degrade stability. In conflict with this consideration, sufficient minimum capacitance is required in order to stabilize the current limit. If the maximum capacitance tolerable for LDO 10 stability and node N1 is smaller than the minimum required capacitance for stability of the current limit, it is impossible to stabilize both simultaneously.
A second set of difficulties arises for a three gain-stage LDO. In this case, we assume for the purposes of example that the error amplifier 20 is a two-stage amplifier, and that node N1 is the second high impedance node of the error amplifier 20. The first high impedance node pole of the amplifier 20 is split by the Miller compensation capacitor Cc. Thus, similar to the case of compensation to a low impedance node as described above, node N1 provides a pole that is not split by the Miller compensation. Thus, it is desirable to keep the capacitance at node N1 at a minimum for LDO 10 stability. On the other hand, sufficient compensation capacitance is required for maintaining current limit loop stability. Again, it may be impossible to compensate both the LDO 10 and current limit loop 22 simultaneously. Additionally, the same trade-offs exist between the degradation of transient response and stability.
One potential solution to these problems using the prior art approach is the addition of a relatively large amount of capacitance at node N2 in an effort to make the pole at this node become dominant. This potential solution is costly in terms of requiring a relatively large die area.
It has been determined that these and other problems result from the fact that the stability of the loops in the circuit are coupled in terms of stability requirements. In this example, the capacitances affecting LDO stability and current limit stability inevitably affect one another. Due to these and other problems, it would be useful and advantageous to decouple the stability requirements of the loops within a circuit having an LDO in particular, and within a circuit having a main loop and a sensing loop in general.